发明名称 Instructions and logic to provide memory access key protection functionality
摘要 Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.
申请公布号 US9411600(B2) 申请公布日期 2016.08.09
申请号 US201314099954 申请日期 2013.12.08
申请人 Intel Corporation 发明人 Anvin H. Peter;Dixon Martin G.
分类号 G06F11/10;G06F9/38;G06F12/14;G06F9/30 主分类号 G06F11/10
代理机构 Nicholson De Vos Webster & Elliott LLP 代理人 Nicholson De Vos Webster & Elliott LLP
主权项 1. A processor comprising: a control register to store a memory protection field; a cache to store cache coherent data in one or more cache lines for one or more memory addresses of a primary storage; a decode stage to decode a first instruction specifying a register operand, an addressing form field for a memory operand to specify said one or more memory addresses, and a memory protection key; and one or more execution units, responsive to said memory protection field having a first value and to said addressing form field of the decoded first instruction having a second value, to: enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing said one or more memory addresses, andfault if a portion of the memory protection key specified by the decoded first instruction does not match one or more stored key values associated with said one or more memory addresses; but wherein said one or more execution units, responsive to said memory protection field having a third value different from said first value, is to generate instead, a legacy address.
地址 Santa Clara CA US