| 摘要 |
PURPOSE: To supply a stable retiming clock even when phase is locked again after the end of clock phase locking. CONSTITUTION: The circuit has a clock distribution buffer 101 giving/receiving a reference clock 12, a variable delay circuit 130 adjusting a delay of an output of the buffer to provide an output of a retiming clock 21, a phase comparator 102 comparing a phase of the reference clock 12 with a phase of the retiming clock 21, a phase coincidence detection circuit 111 providing an output of a phase coincidence signal 23 based on the result of phase comparison, and a control section 120 controlling the delay in the variable delay means. The control section 120 adjusts the delay over a delay in a range between 1/N of one period and one period time of the reference clock 12, sets a delay to be an optimum delay when the phase coincidence signal 23 is outputted at initializing and adjusts the delay as to a delay over a prescribed range based on the optimum delay after the initializing. |
