An LDD lateral DMOS transistor is provided in a lightly-doped epitaxial layer of a first conductivity above a substrate of the same conductivity. A highly-doped buried layer of the first conductivity is provided under the LDD lateral DMOS transistor to relieve crowding of electrical equipotential distribution beneath the silicon surface. In one embodiment, a gate plate is provided above the gate and the gate-edge of the drift region. An optional N-well provides further flexibility to shape electric fields beneath the silicon surface. The buried layer can also reduce the electric field in a LDD lateral diode and improves cathode-to-anode reversed-recovery characteristics. <IMAGE>
申请公布号
DE69224446(D1)
申请公布日期
1998.03.26
申请号
DE1992624446
申请日期
1992.05.05
申请人
SILICONIX INC., SANTA CLARA, CALIF., US
发明人
WILLIAMS, RICHARD K., CUPERTINO, CALIFORNIA 95054, US;CORNELL, MICHAEL E., CAMPBELL, CALIFORNIA 95008, US