Method of manufacturing self-aligned bit-line during EPROM fabrication

摘要

An EPROM device is provided with self-aligned bit-lines. A tunnel oxide layer is formed on a semiconductor substrate. Blanket layers of doped, polysilicon layer, an interelectrode dielectric layer and a blanket polycide layer are formed over the dielectric layer. A TEOS dielectric layer is formed over the blanket polycide layer and a silicon nitride layer. A self-aligned source and drain etching process forms EPROM gate electrode stacks with trench spaces between the stacks in an array. Source/drain dopant ions are implanted in an MDD N+ process between the stacks forming alternating source and drain regions below the spaces between the sidewalls. Spacer dielectric structures are formed adjacent to the sidewalls over the drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling the spaces over the source regions. An additional N+ implant is made between the spacers into the drain regions. A blanket BPTEOS dielectric layer is formed over the stacks, spaces and sidewalls. Drain bit-line openings are etched to the drain regions through the blanket dielectric layer and the tunnel oxide layer over the drain regions between the spacers. A barrier metal layer of titanium/titanium nitride is formed over the drain regions. A conductive metal layer in contact with the drain regions through the bit-line openings is etched to form the metal layer leaving the bit-lines across the device and contacting with the drain regions.