发明名称 |
Buffer system using parity checking of address counter bit for detection of read/write failures |
摘要 |
A data buffer has a storage array that is addressable for read and write operations by an address of n bits that are supplied by a read address counter and a write address counter that each have n+1 bits. The n+1th bit is in effect a counter for passes through the array by the read and write circuits. During a write operation the n+1th bit of the write counter is stored as part of a parity bit for the addressed array location. During a read operation the n+1th bit of the read address counter is entered into a parity checking function on the word read from the addressed location. An errror is signaled if the n+1th bit of the read address counter does not agree with the n+1th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have previously been read. The same entries on a next pass through the array. |
申请公布号 |
US4692893(A) |
申请公布日期 |
1987.09.08 |
申请号 |
US19840685514 |
申请日期 |
1984.12.24 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP. |
发明人 |
CASPER, DANIEL F. |
分类号 |
G06F5/06;G06F5/10;G06F7/78;G06F11/10;H04L13/08;(IPC1-7):G06F11/10 |
主分类号 |
G06F5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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