Storage circuit and data control circuit with address assignment/allocation circuit

摘要

The memory circuit includes an arrangement of memory cells in the form of a matrix, several outer connection lines arranged in accordance with rows and columns of memory cells, and a row redundancy control circuit for compensating for faults in the memory cell arrangement. The row redundancy control circuit includes a group of control memory cells (C11-C14) which has the same number of control memory cells as that of the outer connection lines. The control memory cells stores a binary value relating to the outer connection lines, which are arranged at the end in one direction from the inner connection line, with the error data value. Also included is a group of selectors (SEL1-SEL4) which contain a number of selector switches assigned to the respective control memory cells of the group.