DESIGN STRUCTURE FOR REDUCING POWER CONSUMPTION FOR MEMORY DEVICE

摘要

A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

主权项

1. A method in a computer-aided design system for generating a functional design model of a processor, said method comprising:
detecting memory address information corresponding to accessed data in a first instruction; detecting memory address information corresponding to accessed data in a second instruction; comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction; detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device; executing the second instruction using the accessed data from the first instruction; and detecting an error from the execution of the second instruction.