| 摘要 |
PROBLEM TO BE SOLVED: To provide a pseudo-random signal generating circuit, which is capable of reducing operating FF in number and decreased in circuit scale by enabling the outputs of two false random signal generators having bit widths smaller than the required bit width and being considered as rows and columns so as make them conform to the required bit width by the use of a matrix computation. SOLUTION: A pseudo-random signal generating circuit is equipped with a generator 110, which generates first false random signals with a bit width of a (a is an integer of 1 or larger), a generator 120 which generates second pseudo-random signals with a bit width of b (b is different from a and is an integer of 1 or larger), a matrix-computing unit 130 which enables the first and second false random signals to be subjected to matrix computation and outputs computation result signals having a bit width of (a*b), an N-bit shift register 200, which generates false random signals having a bit width of N (N is a measure of (a*b)), and a subharmonic clock generator 300 for driving a pseudo-random data generator 100. |
