发明名称 Multiple Chirp Generation in a Radar System
摘要 A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.
申请公布号 US2016187462(A1) 申请公布日期 2016.06.30
申请号 US201414586854 申请日期 2014.12.30
申请人 Texas Instruments Incorporated 发明人 Altus Tom;Nayyar Jasbir Singh;Ramasubramanian Karthik;Ginsburg Brian Paul
分类号 G01S7/28;G01S13/02 主分类号 G01S7/28
代理机构 代理人
主权项 1. A radar device comprising: a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having a set of chirp configuration parameter inputs, a set of chirp profile parameter inputs, a chirp address output, and a set of chirp control signal outputs; a chirp configuration storage component having a set of chirp configuration parameter outputs coupled to corresponding inputs of the set of configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output; and a chirp profile storage component having a set of chirp profile parameter outputs coupled to the set of chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.
地址 Dallas TX US