Redundancy scheme for memory circuits

摘要

A redundancy scheme for memory circuits that eliminates the need for physical disconnection or logical deselection of defective elements. The invention does not rehire disabling a defective element and allows it to operate and generate bad data. The circuit is designed such that the redundant element is able to override the defective element. Various approaches to row and column redundancy based on this principal are disclosed for memory circuit such as dynamic and static random access memories. <MATH>