| 摘要 |
A microprocessor-controlled implantable cardiac stimulating device having a normal mode, an intermediate mode, and a backup pacing mode is provided. The device switches from one mode to another in response to the detection of any one of an address error, parity error, opcode error, or watchdog timer error. The microprocessor is shut down during the delivery of a cardioversion or defibrillation shock in order to prevent signals produced by the microprocessor from being subjected to transient electrical signals. The interrupt registers of the microprocessor are also disabled during the delivery of a cardioversion or defibrillation shock. In an alternative embodiment, an implantable cardiac stimulating device is provided with redundant microprocessors in order to detect malfunctions of the microprocessors.
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