发明名称 |
Address enable circuit in synchronous SRAM |
摘要 |
A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level. The address latching circuit is reset when the reset signal indicates a reset so that the synchronized address identifies a disabled address that indicates that memory access to the memory core is disabled and is not reset when the reset signal does not indicate a reset.
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申请公布号 |
US5848022(A) |
申请公布日期 |
1998.12.08 |
申请号 |
US19970850717 |
申请日期 |
1997.05.02 |
申请人 |
INTEGRATED SILICON SOLUTION INC. |
发明人 |
JIANG, YONG H. |
分类号 |
G11C8/06;G11C8/18;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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