发明名称 FUKIHATSUSEIMEMORIKAIRO
摘要 The present invention relates to a precharge/discharge nonvolatile memory circuit for detecting signals output from two bit lines on read-cell and dummy cell sides using a flip-flop circuit, comprising a first row decoder (11) on the read-cell side, a second row decoder (11) on the dummy-cell side, a first column decoder (14-1) on the read-cell side, a second column decoder (14-2) on the dummy-cell side, a read cell (12) selected by the first row decoder (11) and the first column decoder (14-1), a dummy cell (15) selected by the second row decoder (11) and the second column decoder (14-2), first and second precharge transistors (P1, P2) for performing a precharge operation, first and second discharge transistors (D1, D2) for performing a discharge operation, the flip-flop circuit (18), a discharge control circuit (21) for generating a discharge signal, and a precharge control circuit (22) for generating a precharge signal after the discharge signal is generated from the discharge control circuit (21). <IMAGE>
申请公布号 JP2637314(B2) 申请公布日期 1997.08.06
申请号 JP19910219932 申请日期 1991.08.30
申请人 TOSHIBA KK 发明人 MATSUMOTO OSAMU;MIKI KAZUHIKO
分类号 G11C17/00;G11C16/06;G11C16/28;G11C16/30;G11C17/12;H01L27/10 主分类号 G11C17/00
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