| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller configured to calibrate a clock-cycle relationship between a data-strobe signal and a clock signal.SOLUTION: Write-read-validate operations of a memory controller involve varying a delay on a data-strobe signal relative to a clock signal by a multiple of a clock period. A phase detector on a memory chip receives signals, including the clock signal, a marking signal, and the data-strobe signal, from the memory controller, where the marking signal includes a pulse that marks a specific clock cycle in the clock signal. The phase detector uses the marking signal to window the specific clock cycle in the clock signal, and uses the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.SELECTED DRAWING: Figure 3 |
