| 摘要 |
<p>A plurality of disk drive memories are operatively coupled to a plurality of disk drive controllers. The disk drives are operatively grouped and coupled to a plurality of communication busses, each bus being coupled to a respective disk drive controller. A plurality of segment buffers are coupled to the disk drive controllers and a parity error correction system is coupled to the segment buffers. The error correction system is coupled to an input/output circuit through a plurality of buffers and an interface circuit. A processor communicates with the output buffers, the error correction system, and the segment buffers to control the storage and retrieval of data to and from the array of disk drives. The error correction system establishes a plurality of relatively small parity groups among the disk drives, each parity group having a designated parity drive. The number of drives within each parity group is maintained at a substantially reduced number to provide high speed system response to user inputs and changes and to improve system reliability. Data is uniformly distributed among the parity groups and the disk drives therein.</p> |
