发明名称 SCHALTUNGSANORDNUNG ZUR SOLLWERT NSTELLUNG FUER E FRE QUENZABHAENGIGEN DREHZAHLEN MEHRERER IN EINEM FESTEN EIN STELLBAREN DREH HLVERHAELTNIS ZUEINANDER STEHENDER WECHSELSTROMMOTOREN
摘要 1,137,938. Control of several A.C. motors. BORG-WARNER CORP. 3 Oct., 1966 [5 Oct., 1965], No. 44128/66. Heading H2J. In a ratio control system for regulating the speeds of a plurality of motors 10-40 at different stations, the ratio of motor speeds between two adjacent stations may be changed without altering the previously established speed ratios between the remaining stations. A master oscillator 12 supplies timing pulses to digital stages 14-22 each of which controls the ratio between the motors of that stage and those of the succeeding stage. The stage 14 passes pulses to master inverter 26 and to stage 16 at the second station. Inverter 26 regulates slave inverters 28, 29, associated with motors 10, 11. The second stage 16 provides output pulses at a rate which is dependent upon the pulses received over lines 24, 27, to regulate the frequency of master inverter 32 for controlling slave inverter 33 and motor 20. The stage 14 comprises comparator 41 which sends a signal to master inverter 26 and a reset signal to counter 46 when voltages V1, V2, are equal. The counter 46 includes count circuit 47, a circuit 48 for operating circuit 47 instantaneously as each pulse is received over conductor 24, and a gate circuit 49 which sends signals over a plurality of conductors 50 to a digital-to-analog converter 51. The value of voltage V2 depends upon the output of converter 51, whilst the value of voltage V1 is determined by divider network 54. Count circuit 47 is coupled to memory unit 61 which registers the number of pulses passed over conductor 24 to counter 46 before comparator 41 recognizes equality between voltages V1, V2. This number-denoting signal is applied to digital-to-analog converter 63 the output of which determines the voltage on line 27. As long as there is no equality between voltages V1, V2, counter 46 accumulates timing pulses from the master oscillator, the output of converter 51 increasing until the voltages become equal. Count circuit 47 is then reset to zero and an output pulse over line 25 regulates the frequency of the master inverter and the speed of the motors at the first stage. Potentiometer 15, which is connected to converter 63, controls the ratio between stages 14, 16, since the counters 46, 76, receive pulses at the same frequency, and the time at which voltages V3, V4, become equal depends upon the setting of arm 65. Similarly, adjustment of the position of arm 95 correspondingly governs the ratio between stages 16, 18.
申请公布号 DE1538366(B1) 申请公布日期 1971.02.25
申请号 DE19661538366 申请日期 1966.10.04
申请人 BORG WARNER 发明人 GEIS EVERETT R
分类号 D21F7/02;H02P5/50;H03M1/00 主分类号 D21F7/02
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