| 摘要 |
<p>PURPOSE:To form a cell array into a virtual ground structure so as to lessen a non-volatile memory in chip size even if such a trouble that the memory is put in an enhancement state when a memory cell section is excessively erased occurs by a method wherein a specific memory cell is provided. CONSTITUTION:A floating gate 4 is arranged on a semiconductor substrate where a field oxide film is formed through the intermediary of a gate insulating film 3, and a selection gate 8 is provided to the side wall of the floating gate 4. A first impurity diffusion region 6a arranged through a self-aligned manner and a second impurity diffusion region 6b arranged in self-alignment with the selection gate 8. Furthermore, a control gate 9 is provided widthwise traversing the channel of the floating gate 4 at a right angle, and a spacer 13 connected to the selection gate 8 is formed on the side wall of the control gate 9. By this setup, a non-volatile memory of this design can be lessened in chip area.</p> |
