| 摘要 |
The purpose of the present invention is to provide a latch circuit which is strong for software error tolerance. The latch circuit comprises: a first PMOS transistor to pull up a second node in response to a voltage level of a first node; a first NMOS transistor to pull down the second node in response to the voltage level of the first node; a second PMOS transistor to pull up the first node in response to the voltage level of the second node; a second NMOS transistor to pull down the first node in response to the voltage level of the second node; a first separation element to electrically separate the first NMOS transistor from the second node when the first PMOS transistor is turned on; and a second separation element to electrically separate the second NMOS transistor from the first node when the second PMOS transistor is turned on. |
