| 发明名称 | Managing a power state of a processor | ||
| 摘要 | A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt. | ||
| 申请公布号 | US9372526(B2) | 申请公布日期 | 2016.06.21 |
| 申请号 | US201213724594 | 申请日期 | 2012.12.21 |
| 申请人 | Intel Corporation | 发明人 | Bodas Devadatta V.;Mann Eric K. |
| 分类号 | G06F1/32;G06F9/48 | 主分类号 | G06F1/32 |
| 代理机构 | International IP Law Group, P.L.L.C. | 代理人 | International IP Law Group, P.L.L.C. |
| 主权项 | 1. A device for sending a signal indicating an impending interrupt to a processor, wherein the device is configured to: generate a signal indicating that an interrupt is to be sent to a processor of a system; determine a delay for sending the signal to the processor based on a delay for sending the interrupt to the processor, wherein the delay for sending the interrupt to the processor corresponds to a direct memory access (DMA) coalescing procedure in which the interrupt is buffered for a specified interval of time; send the signal to the processor after the delay for sending the signal has elapsed; and send the interrupt to the processor after the delay for sending the interrupt has elapsed. | ||
| 地址 | Santa Clara CA US | ||