| 摘要 |
<p>PURPOSE:To extract the parallel output data in the same sequence of the input data bits providing two shift registers containing serial data input and output terminals respectively to each of two ICs set vertically and having the proper connection between both input and output terminals. CONSTITUTION:A memory means of n/2 (actually 16) bits is provided into a chip 11, and shift registers 12 and 13 contain terminals Si1T and Si2T for serial input of data and terminals Po1, Po2,...,Pon/2 for parallel output of data respec- tively are added. In addition, serial output terminals So1T and So2T are provided to both registers 12 and 13 respectively for serial output of data. For arrangement of external terminals, the terminals Po1, Po2,... of the register 12 are set at a side of the chip 11 with parallel output terminals Po32,...,Po17 of the register 13 arrayed downward at the opposite side of the chip 11 respectively. Thus the serial data input and output terminals of registers 12 and 13 are set on the diagonal lines to each other.</p> |
