发明名称 Layout verification method and layout design unit
摘要 By providing plural layers in which circuit components of an integrated circuit using plural voltages are arranged in accordance with used voltages, separately arranging the circuit component to which a high voltage is applied in a specific layer among the plural layers, recognizing the used voltage for each layer, and performing a layout verification by applying a condition in accordance with the used voltage, it is possible to recognize the circuit component, to which a high voltage is applied, on the layout, and to perform the layout verification using a layout rule in accordance with the used voltage using only the layers used in an actual process without newly generating a dummy layer etc.
申请公布号 US2006225012(A1) 申请公布日期 2006.10.05
申请号 US20050166153 申请日期 2005.06.27
申请人 FUJITSU LIMITED 发明人 DEURA MANABU
分类号 G06F17/50 主分类号 G06F17/50
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