| 摘要 |
<p>Output power control in burst transmitters that comprise a power amplifier stage the gain of which varies according to a power control signal (PCS), an output signal sensing circuit (PS), a detector (DET) that generates a DC voltage signal proportional to the level of the sensed signal and a comparator (COMP) to generate the power control signal (PCS) in proportion to the difference between the DC voltage coming from the detector (DET) and a reference voltage (Vref). The power control signal (PCS) is sampled in a sample-and-hold circuit (SHC) using the active edges of a clock signal (CS), these occurring only at the moments when there are signal bursts to be transmitted and at a time subsequent to the start of each burst greater than the duration of the transient of the DC analogue voltage signal at the output of the detector.</p> |
