| 摘要 |
A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.
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