| 摘要 |
PROBLEM TO BE SOLVED: To prevent the deterioration of handling charge quantity in the final stage of a transfer register and to improve the transfer efficiency of signal transfer from the final stage of the transfer register to an output part by impressing a clock pulse only on a transfer electrode on the storage part of the final stage through a private wiring apart from that for horizontal transfer electrode. SOLUTION: The horizontal transfer electrode 19a of the storage part in the final stage receives a pulse Hϕ1 which is to be received from an input terminal 14 not through a bus line 16 but a private line 18. The phase of the horizontal transfer pulse Hϕ1 reaching the storage part of the final stage differs from that reaching a transfer part in the final stage, and the phase of the pulse reaching the storage part is advanced. This is caused by the transfer of the pulse only to the storage part of the final stage by the private wiring 18. Since the phase advances, handling charge quantity in the final stage can be increased while the transfer efficiency of the signal charge from the storage part in the final stage to an output gate is improved.
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