发明名称
摘要 PROBLEM TO BE SOLVED: To automatically collate an execution result between two CPUs and to make check work efficient by comparing the state of a storage element at the timing of the separation of instruction execution. SOLUTION: Circuit information 101 and a test pattern 102 are input data of a first simulation 105. Then, a result 107 is generated. Circuit information 103 and a test pattern 104 are input data of a second simulation 106. Then, a result 108 is generated. A comparison timing detection means 109 outputs 111 the state of the storage element of a flip flop from the result 107 at the time matched with a retrieval condition being the combination of specified signal values in the result 107. Then, the state of the storage element is similarly outputted 112 from the result 108. A comparison means 113 compares whether both results are the same or not. At that time, time does not have important meaning and only the order relation of the change of the signal becomes the object of comparison.
申请公布号 JP2904172(B2) 申请公布日期 1999.06.14
申请号 JP19960354365 申请日期 1996.12.19
申请人 NIPPON DENKI KK 发明人 MINAMITANI JUNICHIRO
分类号 G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/28
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