发明名称 Method of testing memory device
摘要 A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generates an output upon discrimination that said memory device is satisfying conditions for performing test, and when an output of the entry circuit is generated and a memory arrangement of the memory device is in a write enable state, a gate circuit generates an output to activate a buffer circuit, by which the internal signal is written to the memory arrangement by being connected to a data write input of the memory arrangement via the buffer circuit, then reading the written data to the outside from the memory arrangement, and performing the measurement related to the internal signal by detecting data change points.
申请公布号 US7360128(B2) 申请公布日期 2008.04.15
申请号 US20030402181 申请日期 2003.03.27
申请人 NEC ELECTRONICS CORPORATION 发明人 SHIMOSAKA TOMOKATSU
分类号 G01R31/28;G11C29/00;G11C11/401;G11C29/08;G11C29/50 主分类号 G01R31/28
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