| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem wherein there is a risk of latch-up occurring between the power supply voltage and the ground voltage. SOLUTION: A semiconductor device includes a depression-type PMOS transistor having (1) a P-type substrate, (2) an N-type well, (3) an NMOS transistor, (4) P-type tap, (5) a PMOS transistor, (6) an N-type tap, and further, (7) a parasitic transistor, having a drain connected with low voltage and a source connected with the ground voltage to prevent latch-up due to the low voltage becoming higher than the ground voltage. The device includes the depression-type PMOS transistor where a conductive state keeps the low voltage substantially at the ground voltage, in which a gate is connected substantially with the ground voltage until the risk for the low voltage becoming higher than the ground voltage is no longer observed. COPYRIGHT: (C)2008,JPO&INPIT
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