| 摘要 |
A reconfigurable digital signal processing system includes a serial to parallel converter having at least one delay block and at least one decimation block arranged to convert a first serial signal with a first sampling rate to a multiplicity of parallel subband signals with a second sampling rate. The second sampling rate is less than or equal to the first sampling rate. Processing blocks are arranged to process the subband signals to produce processed signals. A configuration controller is arranged to modify the decimation factor of each decimation block and to load a configuration into the memory of a processing block. A parallel to serial converter comprising at least one expansion block, the parallel to serial converter is arranged to recover from the processed signals a second serial signal with a sampling rate substantially equal to the first sampling rate.
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