| 摘要 |
An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.
|
