| 摘要 |
PURPOSE:To shorten the switching processing time of a process and to obtain a high-speed system, by performing the stand-by processing of a register in parallel to the execution of instruction after the switching processing of the process. CONSTITUTION:A stand-by address register 637 is set by the output of an AND circuit 636. Every time a machine clock is supplied, +1 addition is performed through a +1 circuit 638. Namely, read data 78 which corresponds to a process before execution in the 2nd register stack 62 is outputted. The output of the AND circuit 636, on the other hand, is passed through an OR circuit 640 to obtain a set signal to a memory address register 642. The stand-by area starting address set in the register 642 is increased by four at every time by a +4 circuit 643 and outptted as a main storage address 79. Therefore, the contents which correspond to the procees before execution stored in the 2nd register stack 62 are enqueued in a corresponding stand-by area in a main storage device 1. |
