| 摘要 |
PROBLEM TO BE SOLVED: To provide a multi-DSP(digital signal processor) system easy to design and increasing a processing speed. SOLUTION: This processor is provided with plural DSPs in parallel, and divides operation processing for target digital signal processing to plural operation processing parts to make share and process to respective DSPs. Respective DSPs are connected by buses, and the first DSP among them contains a dual port memory respectively having a write-in port and a read-out port for storing the operation processing result data, and the data read out from the read-out port of the dual port memory of the first DSP through the buses are transmitted to the second DSP. The second DSP performs the prescribed operation processing for the data transmitted from the first DSP. Since the first DSP can control the read-out operation timing of the dual port memory matching with the peculiar timing of the second DSP independent of its write-in operation timing, respective DSPs become to be operated at independent timing, and a design of respective operation programs is facilitated. |
