Vector Operation Core and Vector Processor

摘要

A vector operation core and a vector processor are provided. The vector operation core use two three-input adders and four data negators, so that the data input into the input adders may be flexibly negated. In addition to being provided with the vector operation core, the vector processor also comprises a control unit, which controls a selector and the negators in the vector operation core. The vector processor may simultaneously support butterfly operations in a base 2, base 3 and base 5 fast Fourier transform. The vector operation core may be widely applied to the design of the programmable vector processor in a multimode-compatible mobile terminal chip.

主权项

1. A vector operation core, comprising a first operation branch and a second operation branch; wherein the first operation branch comprises: input ends 1, 2, 3, multiplier 7, an either-or selector 9, negators 11, 12, a three-input adder 15 and an output end 17; and the second operation branch comprises: input ends 4, 5, 6, multiplier 8, an either-or selector 10, negators 13, 14, a three-input adder 16 and an output end 18; the negators 11, 12, 13, 14 are configured to control signs of output data of the negators 11, 12, 13, 14 respectively; wherein
data of the input end 1 is input into one select input end of the either-or selector 9, data of the input ends 2, 3 is input into two input ends of the multiplier 7, and data outputted from the multiplier 7 is divided into two branches which are respectively input into input ends of the negators 11, 13 respectively; data of the input end 6 is input into one select input end of the either-or selector 10, data of the input ends 4, 5 is input into two input ends of the multiplier 8, and data outputted from the multiplier 8 is divided into two branches which are respectively input into input ends of the negators 12, 14; data outputted from the selector 9, negators 11, 12 is respectively input into three input ends of the adder 15; data outputted from selector 10, negators 13, 14 are respectively input into three input ends of the adder 16; data output from the adder 15 is divided into two branches which are respectively input into the output 17 and the other select input end of the selector 9; data output from the adder 16 is divided into two branches which are respectively input into the output 18 and the other select input end of the selector 10.