发明名称 CLOCK MULTIPLYING CIRCUIT
摘要 PURPOSE:To obtain a two-multiplied clock extending over a wide range of an input clock frequency by combining an integration circuit for integrating an input clock and a folding circuit. CONSTITUTION:A clock of frequency f0 inputted to an input terminal 13 is integrated by an integration circuit 10, converted to a triangular wave 14 and provided to a folding circuit 11. Subsequently, the folding circuit 11 turns back the negative part to positive basing on ''0''V being a mean level of the triangular wave 14, as a reference, obtains a triangular wave 15 having a frequency of twice the triangular wave 14 and provides it to a comparing circuit 12. The comparing circuit 12 which receives it compares the triangular wave 15 with ''0'' voltage, converts it to a clock pulse of frequency of 2f0 and outputs it to an output terminal 16. By forming in this way, a two-multiplied clock is obtained extending over a wide range of an input clock frequency.
申请公布号 JPS59161118(A) 申请公布日期 1984.09.11
申请号 JP19830035321 申请日期 1983.03.04
申请人 NIPPON DENKI KK 发明人 KURIYAMA NOBUMI
分类号 H03K5/00 主分类号 H03K5/00
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