发明名称 PLL CIRCUIT
摘要 PURPOSE:To avoid the response to an undesired dynamic range even when the center frequency is lowered by adding the 1st constant current source output current and the output current of a differential amplifier so as to use the current sum thereby controlling an oscillator. CONSTITUTION:When the same voltage signal as a signal Vref is inputted to an input terminal 1A, the differential amplifier is in the balanced state, an input voltage VCONT to a voltage controlled oscillator VCO 6 is expressed as VCONT =1.5IRL (RL is a resistance of a resistor 5), an oscillated frequency fC is obtained, which is the center frequency to the PLL circuit. When the input voltage to the input terminal 1A is larger than the voltage Vref, the collector current ICB of a pnp transistor 2B is increased in response to the difference voltage and when the differential amplifier is switched completely, the relation of VCONT=2IRL is obtained. When the input voltage to the input terminal 1A is smaller than the voltage Vref and the differential amplifier is switched completely finally, the relation of VCONT=IRL is obtained. When the oscillated frequency of the oscillator VCO6 is proportional to the input voltage VCONT, since the input voltage changes from the value IRL to the value 2IRL, the oscillated frequency is limited from 2/3fC to 4/3fC.
申请公布号 JPS62183217(A) 申请公布日期 1987.08.11
申请号 JP19860023717 申请日期 1986.02.07
申请人 HITACHI LTD 发明人 YAMAZAKI SHIGERU;NODA TSUTOMU
分类号 H03L7/093;H03L7/06 主分类号 H03L7/093
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