| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit and the control method of the PLL circuit for reducing the frequency error of an output signal for a reference signal and outputting small spurious output signal. SOLUTION: DDS 11a divides a reference frequency signal (f0 ) to be output to PD 12, which makes a phase reference signal (fr ) output from DDS 11a a reference phase. DDS 11b sets a signal output from VCO 13 to a frequency corresponding to a frequency set by DDS 11a, and the dividing signal is output to PD 12. PD 12 detects a phase difference between the above phase reference signal and the dividing signal to be output to VCO 12, which corrects a phase fluctuation part on the basis of the detected phase difference to output an output signal (fv ) whose frequency is maintained constant. |
