发明名称 Method and intelligent slave device transfer control unit for implementing seamless error resumption in a shared memory bus structure
摘要 A method and apparatus are provided for implementing seamless error resumption in a shared memory bus structure. Controls and data are stored for each read operation and each write operation. Each read operation and each write operation is monitored to determine when an error has occurred for either a read operation or a write operation. When an error has occurred for the read operation or the write operation, the error is suppressed and the stored controls and data are gated to continue the read operation or the write operation.
申请公布号 US7191366(B2) 申请公布日期 2007.03.13
申请号 US20040787643 申请日期 2004.02.26
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CARR JEFFERY DEAN
分类号 G06F12/00;G06F11/07 主分类号 G06F12/00
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