发明名称 METHOD OF FORMING A VOLTAGE REGULATOR AND STRUCTURE THEREFOR
摘要 A voltage regulator and a method forming the same are provided to reduce starting time and power consumption of the voltage regulator, by charging a capacitor rapidly using a high current and maintaining charges on the capacitor using a low current. A voltage regulator(20) includes an output(25), an error amplifier(31), a first input and a charging circuit. The output controls an output voltage as a target value. The error amplifier receives a sensing signal indicating the output voltage, and receives a reference signal, and controls the sensing signal to be equal to the reference signal in response to the reference signal. The first input is connected to a capacitor(16) and receives the reference signal. The charging circuit is connected to the first input, and charges the capacitor with a first current during a first time, and charges the capacitor with a second current after the first time. The first current is higher than the second current.
申请公布号 KR20070117501(A) 申请公布日期 2007.12.12
申请号 KR20070056006 申请日期 2007.06.08
申请人 SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. 发明人 DOW STEPHEN W.;MANAPRAGADA PRAVEEN;MOELLER DAVID F.
分类号 G11C5/14;G11C7/06 主分类号 G11C5/14
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