| 摘要 |
PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory element capable of securing misalignment margin in contact hole formation in an active area even on a high integrated memory element and decreasing junction capacitance and leak current. SOLUTION: A spacer 20a comprising a substance having a high corrosion selection ratio for an interlayer insulation film 26 is formed on the side wall of a gate electrode 16, and the contact hole exposed between the gate electrodes 16 can be formed by a self matching method by forming the upper part of the gate electrode and the upper part of the substrate forming the source and drain areas in high melting point metal silicide films 18a, 22. In addition, after the inside of the contact hole is filled with a metal 28 such as tungsten, an impurity area 32 is formed only on the lower part of the gate electrode 16 by ion injection over the whole active area.
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