Clock structure for reducing power consumption on wireless mobile devices

摘要

A mobile device (300) includes an oscillator (310) to generate a reference clock signal, a phase-locked loop (PLL) circuit (320) to generate a PLL output clock signal, a transceiver (330), a system-on-a-chip (SOC) (340) including a processor (342) and a number of other modules, and a control logic (350). The transceiver (330) generates a status control signal that indicates whether the transceiver (330) is in an active state or in an idle state. The control logic (350) receives the status control signal, and in response thereto, selectively enables/disables the PLL circuit (320), selectively routes either the reference clock signal or the PLL output clock signal to the processor (342) and/or the other modules of the SOC (340), and/or selectively routes either an idle clock signal or the PLL output clock signal to the transceiver (330).

主权项

1. A mobile device, comprising:
an oscillator to generate a reference clock signal; a phase-locked loop (PLL) circuit to generate a PLL clock signal in response to the reference clock signal, wherein the PLL circuit includes a control terminal responsive to a status control signal; a transceiver including a clock input terminal, and including an output terminal to generate the status control signal, wherein the status control signal indicates whether the transceiver is in an active state or in an idle state; a system-on-a-chip (SOC) including a clock input terminal; and control logic to selectively disable the PLL circuit in response to the status control signal and to selectively route the PLL clock signal to the clock input terminal of the transceiver and to the clock input terminal of the SOC in response to the status control signal, wherein the control logic comprises: a first multiplexer including a first input terminal to receive the reference clock signal, a second input terminal to receive the PLL clock signal, a control terminal to receive the status control signal, and an output terminal coupled to the clock input terminal of the SOC; and a second multiplexer including a first input terminal to receive an idle clock signal, a second input terminal to receive the PLL clock signal, a control terminal to receive the status control signal, and an output terminal coupled to the clock input terminal of the transceiver.