发明名称 Integrated circuit with partially used register bank
摘要 The integrated circuit (1) has at least a processor (2), a bank of registers (4) addressed by the processor and an address bus (3) to convey an associated address to a register in the bank (4) by the processor (2). The register bank (4) includes a combinatory logic circuit (302) between, at least an address input of a memory (301) for the bank (4), and the bus address to modify the physical address of the register in the memory (301). The address bus (13) is used by several peripherals (5-12) each having equal access to the register bank (4). The portable card (10) has an interface which receives external signals (VCC,CLK,RST) representing commands applied to the its microcircuits, and input/output signals (I/O) representing data for processing by the microcircuit. In addition the card includes a supervisory system., which monitors during a given time period the application from the exterior of at least one of its commands. The system is designed to detect an abnormal repeated application of this command or of commands with respect to a predefined criteria and to selectively inhibit , as a function of this detection, the processing by the microcircuit of the data received. The supervised controls include the zero reset (RST) and/or the clock signal (CLK), and the monitored time period is
申请公布号 FR2775089(A1) 申请公布日期 1999.08.20
申请号 FR19980002117 申请日期 1998.02.18
申请人 SGS THOMSON MICROELECTRONICS SA 发明人 RAMANADIN BERNARD
分类号 G06F9/30;G06F9/318;(IPC1-7):G06F12/02 主分类号 G06F9/30
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