| 摘要 |
PURPOSE:To prevent malfuction and to attain high speed operation, by respectively providing an MISFET between each word line and ground potential. CONSTITUTION:To gates of MISFET Q1-Q3 provided between word lines WL1-1-DWL1-2 and ground potential, a timing signal phiwl' formed at the next circuit is applied in common. A timing generating circuit (phiwl-G) forms a timing signal phiwl which is at inverse phase with the timing signal phix and at low level for the word line selecting period. This signal phiwl is brought to low level with a circuit consisting of MISFET Q5-Q8 so that the MISFET Q1-Q3 are turned off for a prescribed period. A node N1 is precharged with the timing signal phi' through the MISFET Q4. When a signal phiPA rises to a high level, the MISFET Q5 and Q7 turn on to bring the nodes N1 and N2 to a low level. Thus, since the MISFET Q8 turns off, the timing signal phiwl' is restored to a low potential. |
