发明名称 |
DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS |
摘要 |
A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. |
申请公布号 |
US2013334651(A1) |
申请公布日期 |
2013.12.19 |
申请号 |
US201213525642 |
申请日期 |
2012.06.18 |
申请人 |
DORIS BRUCE B.;PONOTH SHOM;KHARE PRASANNA;LIU QING;LOUBET NICOLAS;VINET MAUD;INTERNATIONAL BUSINESS MACHINES CORPORATION;STMICROELECTRONIC, INC.;COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIESALTERNATIVES |
发明人 |
DORIS BRUCE B.;PONOTH SHOM;KHARE PRASANNA;LIU QING;LOUBET NICOLAS;VINET MAUD |
分类号 |
H01L29/06;H01L21/762 |
主分类号 |
H01L29/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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