发明名称 SHIFT REGISTER
摘要 PURPOSE:To curtail the number of elements of an LSI by connecting in a multistage the circuits connected to a resistance of a memory circuit of the next stage, respectively so as to be operated by a clock given to a differential circuit for switching current sources of an oven stage and an odd stage of this circuit. CONSTITUTION:In the first and the second NPN bipolar transistors 10, 11 of a memory circuit to which a positive feedback is applied by an ECL (emitter coupling type logic circuit) and a resistance, the third transistor 12 whose base and emitter are common, and the fourth transistor 13 whose base and emitter are common are added to the first transistor 10 and the transistor 11, respectively. Also, collectors of the third and the fourth transistor 11, respectively. Also, collectors of the third and the fourth transistors 12, 13 are connected to resistances 8, 9 of the memory circuit of the next stage, and this circuit is connected in a multistage, provided with a differential circuit for switching the current sources of an even stage and an odd stage of this circuit, and operated by a clock given to the differential circuit. In such a way, as for the number of elements per a shift register unit circuit, two pieces of bipolar transistor and one piece of constant-current source are curtailed, and a high integration of various LSIs can be realized.
申请公布号 JPH01307999(A) 申请公布日期 1989.12.12
申请号 JP19880139977 申请日期 1988.06.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAKIYAMA SHIRO;AONO KUNITOSHI
分类号 G11C19/28 主分类号 G11C19/28
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