| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To support a plurality of different types of processors which are connected to a plurality of memory arrays and a plurality of input/output devices via one or more input/output buses. <P>SOLUTION: A multiprocessor system includes a plurality of microprocessors, each of which has a cache for data (D), a cache for a command (D), a plurality of memory ports and an input/output unit. In this multiprocessor system, a memory control unit 50 in each microprocessor consists of a switch network 54, cache interface circuits 55 and 56, an input/output interface circuit 57, a memory port interface circuit P, a switch arbitration means 58 for conducting arbitration for the switch network, and a port arbitration means PAU for conducting arbitration for the memory port. The switch arbitration means gives dynamic priority to each device and changes peculiar priority. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
