发明名称 |
Memory component with pattern register circuitry to provide data patterns for calibration |
摘要 |
A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. |
申请公布号 |
US9367248(B2) |
申请公布日期 |
2016.06.14 |
申请号 |
US201514745746 |
申请日期 |
2015.06.22 |
申请人 |
Rambus Inc. |
发明人 |
Hampel Craig E.;Perego Richard E.;Sidiropoulos Stefanos;Tsern Ely K.;Ware Frederick A. |
分类号 |
H04L7/033;G06F3/06;G11C7/10;G11C7/22;G11C11/4078;G06F12/02;G11C11/406;G11C21/00;H04L7/00 |
主分类号 |
H04L7/033 |
代理机构 |
The Neudeck Law Firm, LLC |
代理人 |
The Neudeck Law Firm, LLC |
主权项 |
1. A controller to control operations of a memory component, the controller comprising;
a first circuit to transmit commands to the memory component, the commands including a read command that specifies data to be accessed from a memory core of the memory component; a second circuit to receive data sent by the memory component via an external bus, the data sent by the memory component in response to the read command; calibration circuitry, operable during calibration, to receive at least a first data pattern and a second data pattern from the memory component, the first data pattern and the second data pattern being provided from pattern register circuitry in the memory component, wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the memory component onto the external bus in response to one of the commands. |
地址 |
Sunnyvale CA US |