发明名称 DIGITAL SIGNAL PROCESSING SYSTEM
摘要 PURPOSE:To prevent the extension of operation error and deterioration in S/N and to simplify circuit, by attenuating output gain at the final stage and making the operation for gain adjustment of a digital filter with a figure corresponding to a large signal level. CONSTITUTION:When a differential equation of a digital attenuation equalizer by means of a digital filter is expressed as equation (1), coefficients a0, a1, a2 in equation (1) are replaced as a0=A0K, a1=A1K, and a2=A2K, and the result of replacement is divided by K, resulting in equation (2a). When the output gain of the digital filter is attenuated, since K is smaller than 1, Yn in equation (2a), i.e. an output obtained from an adder 19 is greater than the Yn. The Yn of the adder 19 is multiplied by K at a multiplier 20 to obtain a new output signal Yn and this is given to an output terminal 7, allowing the operation at a greater signal level. Thus, signal processing can be made without extension of operation error and deterioration in S/N.
申请公布号 JPS57125514(A) 申请公布日期 1982.08.04
申请号 JP19810011910 申请日期 1981.01.29
申请人 NIPPON VICTOR KK 发明人 KASUGA MASAO;TSUCHIKANE YOSHIYUKI
分类号 H03G3/02;G11B20/10;H03H17/00;H03H17/02;H03H17/04 主分类号 H03G3/02
代理机构 代理人
主权项
地址