| 摘要 |
An apparatus multiplies a first and a second binary polynomial X(t) and Y(t) over GF(2), where an irreducible polynomial M<SUB>m</SUB>(t)=t<SUP>m</SUP>+a<SUB>m-1</SUB>t<SUP>m-1</SUP>+a<SUB>m-2</SUB>t<SUP>m-2</SUP>t<SUP>m-2</SUP>+ . . . +a<SUB>1</SUB>t+a<SUB>0</SUB>, and where the coefficients a<SUB>i </SUB>are equal to either 1 or 0, and m is a field degree. The degree of X(t)<n, and the degree of Y(t)<n, and m<=n. The apparatus includes a digit serial modular multiplier circuit coupled to supply a multiplication result of degree >=m of a multiplication of the first and second binary polynomials. The digit serial modular multiplier circuit includes a first and second register, each being <=n bits. A partial product generator circuit multiplies a portion of digit size d of contents of the first register and contents of the second register. The partial product generator is also utilized as part of a reduction operation for at least one generic curve.
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