发明名称 Method for forming interconnect for integrated circuits
摘要 According to the present invention, a thin conductive layer is formed over an underlying structure in an integrated circuit. The underlying structure can be either a semiconductor substrate or an interlevel interconnect signal line. An insulating layer is deposited over the device. The insulating layer is patterned and etched in order to expose a portion of the underlying conductive layer and to define an interconnect signal line. When the signal line locations are etched away, the thin conductive layer acts as an etch stop and protects the underlying structure. A metal refill process can be used to then form interconnects and contacts within the etched interconnect lines. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper surface of the insulating layer in which they are formed.
申请公布号 US5200880(A) 申请公布日期 1993.04.06
申请号 US19910808600 申请日期 1991.12.17
申请人 SGS-THOMSON MICROELECTRONICS, INC. 发明人 HUANG, KUEI-WU
分类号 H01L21/3205;H01L21/768;H01L23/52 主分类号 H01L21/3205
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