Phase compensation circuit of digital processing PLL

摘要

The present invention is to provide a phase compensation circuit of a DPPLL capable of hitless switching during switching the system clock, by exact matching frequency and phase of the DPPLL about phase difference which is less than minimum differential phase which may be detectable the way of digital and by distinguishing phase difference about the other party clock such that each clock unit commonly has the clock generated from the pair of clock units, alternatively and by switching the system clock in case that there is no difference after distinguishing, in the clock supplying system using the pair of lock units which have the phases that is asynchronized to the reference clock.