| 摘要 |
An open digit line memory device includes a memory array. The memory array includes a plurality of memory cells. The memory cells are grouped into sub-arrays. Each of the sub-arrays includes a plurality of digit lines. The digit lines from adjacent sub-arrays connect to a plurality of sense amplifiers. The sense amplifiers located next to the edges of the memory array connect to dummy digit lines. The dummy digit lines are connected to a fixed voltage during a normal mode. During a test mode, the fixed voltage is replaced by a variable voltage so that the all of the sub-arrays, including the sub-arrays at the edges, can be equally stressed during the test mode.
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